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| W741E260 4-BIT FLASH EPROM MICROCONTROLLER Table of Contents-GENERAL DESCRIPTION .............................................................................................................................. 2 FEATURES...................................................................................................................................................... 2 PIN CONFIGURATION.................................................................................................................................... 4 PIN DESCRIPTION ......................................................................................................................................... 5 BLOCK DIAGRAM........................................................................................................................................... 6 FUNCTIONAL DESCRIPTION ........................................................................................................................ 7 ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 37 DC CHARACTERISTICS............................................................................................................................... 37 AC CHARACTERISTICS............................................................................................................................... 39 PAD ASSIGNMENT AND POSITIONS.......................................................................................................... 39 TYPICAL APPLICATION CIRCUIT................................................................................................................ 41 INSTRUCTION SET TABLE .......................................................................................................................... 42 PACKAGE DIMENSIONS.............................................................................................................................. 93 -1- Publication Release Date: March 1998 Revision A2 W741E260 GENERAL DESCRIPTION The W741E260 is a high-performance 4-bit microcontroller (C) that provides an LCD driver and the flash EEPROM for the program memory. The device contains a 4-bit ALU, two 8-bit timers, two dividers (for two oscillators) in dual-clock operation, a 32 x 4 LCD driver, and five 4-bit I/O ports (including 1 output port for LED driving). There are also five interrupt sources and 8-level subroutine nesting for interrupt applications. The W741E260 operates on very low current and has three power reduction modes, hold mode and stop mode in single-clock operation and the dual-clock slow operation, which help to minimize power dissipation. This chip is available for W741C250 and W741C260 bodies, which can be selected by option code. The W741E260 is suitable for end product manufacturer engineering testing and earlier samples before mass production. FEATURES * Operating voltage: 2.4V to 5.5V (LCD drive voltage: 3.0V, or 4.5V) * Crystal/Ceramic oscillator: up to 4 MHz * RC oscillator: up to 4 MHz * Dual-clock operation is selected by code option * Main oscillator - Crystal or RC oscillation circuit can be selected by code option - In crystal mode, high-frequency (400 KHz to 4 MHz) or low-frequency (32.768 KHz) oscillation should be selected by code option - In RC mode, attention must be paid to the high/low frequency oscillation option, because the LCD driver frequency and the ROM code emulation time are related to this option. * Sub-oscillator - Connect to 32768 Hz crystal only - Used in dual-clock operation * Memory - 2048 x 16-bit program flash EEPROM (including 2K x 4-bit look-up table) - 128 x 4-bit data RAM (including 16 working registers) - 32 x 4 LCD data RAM * 21 input/output pins - - - - Ports for input only: 2 ports/8 pins Input/output ports: 2 ports/8 pins High sink current for LED driving: 1 port/4 pins MFP output pin: 1 pin (MFP) * Power-down mode - Hold function: no operation (excluding main oscillator and sub-oscillator) - Stop function: no operation (excluding sub-oscillator) -2- W741E260 - Dual-clock slow operation mode: system is operated by the sub-oscillator (FOSC = Fs and Fm is stopped) * Five types of interrupts - Four internal interrupts (Divider0, Divider1, Timer0, Timer1) for W741C260 body; three internal interrupts (Divider0, Timer0, Timer1) for W741C250 body. - One external interrupt (RC Port) for W741C260 body; two external interrupts (RC port and INT pin) for W741C250 body. * LCD driver output - 32 segment x 4 common - Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) driving mode can be selected - LCD driver output pins can be used as DC output port by code option - Clock source can be main oscillator clock in the single-clock operation mode, or sub-oscillator clock in the dual-clock operation mode; operation mode is selected by code option * MFP output pin - Output is software selectable as modulating or nonmodulating frequency - Works as frequency output specified by Timer 1 * Two built-in 14-bit frequency dividers - Divider0: the clock source is the output of the main oscillator - Divider1: the clock source is the output of the sub-oscillator * Two built-in 8-bit programmable countdown timers - Timer 0: one of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected - Timer 1: includes an auto-reload function and one of two internal clock frequencies (FOSC or FOSC/64) can be selected, or falling edge of pin RC.0 can be selected (output through MFP pin) * Built-in 18/14-bit watchdog timer selectable for system reset - Enable/Disable the watchdog timer can be controlled by command or by option code; the control source (command or option code) can be determined by another option code * Powerful instruction set: 118 instructions for W741C260 body 116 instructions for W741C250 body * 8-level subroutine (include interrupt) nesting * Up to 1 S instruction cycle (with 4 MHz operating frequency) * Packaged in 80-pin QFP -3- Publication Release Date: March 1998 Revision A2 W741E260 PIN CONFIGURATION O X O U T 2 X XU X // V RRMI R IO I A A F NE NN T ND NN 1 0 PTSC1 1CDC2 VV M DDDD O DNHHDD EC1212 V D D 3 S E G 3 1 S E G 3 0 S E G 2 9 S E G 2 8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 RA2 RA3 RB0 RB1 RB2 RB3 RC0 RC1 RC2 RC3 RD0 RD1 RD2 RD3 RE0 RE1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 NNRRVVDCC CCEESPAOO 2 3 SPT MM A32 C O M 1 C O M 0 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9 S E G 1 0 SN EC G 1 1 -4- W741E260 PIN DESCRIPTION SYMBOL XIN1 XOUT1 XIN2 XOUT2 RA0 to RA3 RB0 to RB3 RC0 to RC3 RD0 to RD3 RE0 to RE3 MFP I/O I O I O I/O I/O I I O O FUNCTION Input pin for main-oscillator. Connected to crystal or resistor to generate system clock by code option. Output pin for main-oscillator. Connected to crystal or resistor to generate system clock by code option. Input pin for sub-oscillator. Connected to 32.768 KHz crystal. Output pin for sub-oscillator with internal oscillation capacitor. Connected to 32.768 KHz crystal. Input/Output port. Input/output mode specified by port mode 1 register (PM1). Input/Output port. Input/output mode specified by port mode 2 register (PM2). 4-bit port for input only. Each pin has an independent interrupt capability. 4-bit port for input only. Output port only. This port provides high sink current to drive LEDs. Output pin only. This pin can output modulating or nonmodulating frequency, or Timer 1 clock output specified by mode register 1 (MR1). System reset pin with pull-high resistor. External interrupt pin with pull-high resistor. This pin is bonding option for the W741C250 body. LCD segment output pins. Also can be used as DC output ports specified by option codes. O LCD common signal output pins. Static COM0 COM1 COM2 COM3 Used Not Used Not Used Not Used 1/2 Duty Used Used Not Used Not Used 1/3 Duty Used Used Used Not Used 1/4 Duty Used Used Used Used RES INT SEG0 to SEG31 COM0 to COM3 I I O The LCD alternating frequency can be selected by code option. DH1, DH2 VDD1, VDD2, VDD3 I I Connection terminals for voltage doubler (halver) capacitor. Positive (+) supply voltage terminal. Refer to Functional Description. -5- Publication Release Date: March 1998 Revision A2 W741E260 Pin description, continued SYMBOL VDD VSS VPP MODE DATA I/O I I I I I/O Positive power supply (+). Negative power supply (-). FUNCTION Voltage control pin for the flash EEPROM programming, erasing and verifying. This pin has a built-in pull-low resistor. Mode selection pin for the flash EEPROM programming, erasing and verifying. This pin has a built-in pull-low resistor. Data I/O pin for the flash EEPROM programming and verifying. This pin has a built-in pull-low resistor. BLOCK DIAGRAM SEG0 to SEG31 COM0 to COM3 VDD1 to 3 DH1 to 2 RAM (128 x 4) LCD DRIVER PORT RA VPP DATA MODE Flash EEPROM (2048 x 16) (look_up table 2K x 4) +1(+2) RA0 to 3 ACC PORT RB RB0 to 3 ALU PORT RC PC RC0 to 3 Central Control Unit IEF HEF EVF SCR MR1 PEF SEF PR PM0 PORT RD RD0 to 3 STACK (8 Levels) HCF PSR0 MR0 PORT RE RE0 to 3 . . . SEL MUX MFP Timer 0 (8-bit) Timer 1 (8-bit) Modulation Frequency Pulse Divider 1 (13/14-bit) VDD Watchdog Timer (4-bit) Divider 0 (14-bit) Timing Generator VSS INT RES XIN1 XOUT1 XIN2 XOUT2 -6- W741E260 FUNCTIONAL DESCRIPTION Program Counter (PC) Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses ofthe 2048 x 16 on-chip flash EEPROM containing the program instruction. When the jump or subroutine call instructions or the interrupt or initial reset conditions are to be executed, the address corresponding to the instruction will be loaded into the program counter. The format used is shown below. ITEM Initial Reset INT 0 (Divider0) INT 1 (Timer 0) INT 2 (Port RC) INT 3 (Divider1 for W741C260; INT pin for W741C250) INT 4 (Timer 1) JMP Instruction Subroutine Call ADDRESS 000H 004H 008H 00CH 014H 020H XXXH XXXH INTERRUPT PRIORITY 1st 2nd 3rd 4th 5th - Stack Register (STACK) The stack register is organized as 11-bit x 8 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. When the stack register is pushed over the eighth level, the contents of the first level will be lost. In other words, the stack register is always eight levels deep. Program Memory (flash EEPROM) The flash EEPROM is used to store program codes; the look-up table is arranged as 2048 x 4 bits. The first three quarters of flash EEPROM (000H to 5FFH) are used to store instruction codes only, but the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements. There are two registers (TABL and TABH) to be used in look-up table addressing and they are controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is executed, the contents of the look-up table location address specified by TABH, TABL and ACC will be read and transferred to the data RAM. Refer to the instruction table for more details. The organization of the program memory is shown in Figure 1. -7- Publication Release Date: March 1998 Revision A2 W741E260 16 bits 000H TABH TABL ACC -xxx xxxx xxyy 2048 address Offset 011x xxxx xxxx ROM address = 600H + Offset/4 600H 3 2 1 0 This area can be used to store both instruction code and look-up table Each element (4 bits) of the look-up table 7FFH 2048 x 16-bit Figure 1. Program Memory Organization Data Memory (RAM) 1. Architecture The static data memory (RAM) used to store data is arranged as 128 x 4 bits. The data memory can be addressed directly or indirectly. The organization of the data memory is shown in Figure 2. 4 bits 00H : 0FH Working Register 128 address 7FH 128 x 4-bit Figure 2. Data Memory Organization -8- W741E260 The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers (WR). The other data memory is used as general memory and cannot operate directly with immediate data. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next section. 2. Page Register (PAGE) The page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 PAGE Note: R/W means read/write available. 2 R/W 1 R/W 0 R/W Bit 3 is reserved. Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits: 000 = Page 0 (00H - 0FH) 001 = Page 1 (10H - 1FH) 010 = Page 2 (20H - 2FH) 011 = Page 3 (30H - 3FH) 100 = Page 4 (40H - 4FH) 101 = Page 5 (50H - 5FH) 110 = Page 6 (60H - 6FH) 111 = Page 7 (70H - 7FH) Accumulator (ACC) The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers. Arithmetic and Logic Unit (ALU) This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions: * Logic operations: ANL, XRL, ORL * Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3 * Shift operations: SHRC, RRC, SHLC, RLC * Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. Otherwise CF can be stored or be read out by executing MOVA R, CF or MOV CF, R. -9- Publication Release Date: March 1998 Revision A2 W741E260 Clock Generator The W741E260 provides two oscillation circuits, main-oscillator and sub-oscillator. The main-oscillator can select the crystal or RC oscillation circuit by option codes to generate the system clock through external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be connected to XIN1 and XOUT1, and a capacitor must be connected if an accurate frequency is needed. When the oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32 KHz) can be selected for the system clock by means of option codes. If the RC oscillator is used, a resistor must be connected to XIN1 and XOUT1, and the high/low frequency clock option must be selected to suit the operation frequency. The sub-oscillator must be connected to a 32.768 KHz crystal through XIN2 and XOUT2 external pins when the dual-clock operation mode is selected by option code. The connection is shown in Figure 3. One machine cycle consists of a four-state system clock sequence and can run up to 1 S with a 4 MHz system clock. XIN1 Crystal 32 KHz or 400K to 4MHz or Resistor XOUT1 Crystal 32 KHz XIN2 XOUT2 Figure 3. System Clock Oscillator Configuration Dual-clock operation This operation mode is selected by code option. In the dual-clock mode, the clock source of the LCD frequency selector should be the sub-oscillator clock (32768 Hz) only. But in the single-clock mode, the clock source of the LCD frequency selector will be Fm or Fm/32 (Fm: main oscillator clock). So when the STOP instruction is executing, the LCD will be turned off in the single-clock mode; but the LCD will keep working in the dual-clock mode. In this dual-clock mode, the normal operation is performed by generating the system clock from the main-oscillator clock (Fm). As required, the slow operation can be performed by generating the system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation is performed by resetting or setting the bit 0 of the system clock control register (SCR). If the SCR.0 is reset to 0, the clock source of the system clock generator is the main-oscillator clock; if the SCR.0 is set to 1, the clock source of the system clock generator is the sub-oscillator clock. In the dual-clock mode, the main-oscillator can stop oscillating when the STOP instruction is executing or the SCR.1 is set to 1. But in the single-clock mode, only the STOP instruction can stop the main-oscillator oscillating, because the SCR would be disabled in the single-clock mode. Therefore, in single-clock mode, the clock source of the system clock generator is the main-oscillator clock (FOSC = Fm). When the SCR is set or reset, we must pay attention to the following: 1. X000B X011B: Disable the main-oscillator (Fm) should not be done simultaneously with changing the system clock source (FOSC) from Fm to Fs. The FOSC should be changed first from Fm to Fs before the main-oscillator (Fm) is disabled. The correct sequence is: X000BX001BX011B. - 10 - W741E260 2. X011B X000B: Enabling the main-oscillator (Fm) should not be done simultaneously with changing the FOSC from Fs into Fm. The main-oscillator (Fm) should be enabled first before a delay subroutine is called to allow the main-oscillator to oscillate stably. The FOSC can now be changed from Fs into Fm. The correct sequence is therefore X011BX001Bdelay subroutineX000B. The suggested delay for Fm is 20 mS for 455 KHz ceramic resonator and 10 mS for 4 MHz crystal. We must remember that the X010B state is inhibitive, because it will induce a system shutdown. The organization of the dual-clock operation mode is shown below. Mask Option (High/Low Freq.) SCR.0 XIN1 XOUT1 SCR.1 Fm Fs enable/disable HOLD Main Oscillator Fosc System Clock Generator Divider 0 T1 T2 T3 T4 Mask Option (High/Low Freq.) Fosc/32 XIN2 XOUT2 Mask Option (Single/Dual Clock) Fosc Sub-oscillator LCD Frequency Selector Mask Option (Single/Dual Clock) FLCD enable/disable Divider 1 INT4 HCF.4 SCR.3 (14/13 bit) Figure 4. The Dual Clock Operation Mode Control Diagram 3 SCR Note: W means write only. 2 1 W 0 W W Bit 0 = 0 Main oscillator is selected (Fosc = Fm) = 1 Sub-oscillator is selected (Fosc = Fs) Bit 1 = 0 Enable Fm = 1 Disable Fm Bit 2 Reserved = 1 13-bit Divider1 is selected Bit 3 = 0 14-bit Divider1 is selected - 11 - Publication Release Date: March 1998 Revision A2 W741E260 Dual clock operation mode: - Sub-oscillator enable - SCR.0 = 0, FOSC = Fm - Flcd = Fs, in STOP mode LCD work continue Single clock operation mode: - Sub-oscillator disable - SCR not use, Main oscillator enable, FOSC = Fm - Flcd = FOSC (FOSC/32), in STOP mode LCD off Divider Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts. When the main oscillator starts action, the Divider0 is incremented by each clock (FOSC). When an overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). The interrupt is executed if the Divider0 interrupt enable flag has been set (IEF.0 = 1), and the hold state is terminated if the hold release enable flag has been set (HEF.0 = 1). The last 4-stage of the Divider0 can be reset by executing a CLR DIVR0 instruction. If the main oscillator is connected to the 32768 Hz crystal, the EVF.0 will be set to 1 periodically at each 500 mS interval. If the sub-oscillator is enabled, the Divider1 is incremented by each clock (Fs). When an overflow occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). The interrupt is executed if the Divider1 interrupt enable flag has been set (IEF.4 = 1), and the hold state is terminated if the hold release enable flag has been set (HEF.4 = 1). There are two time periods (250 mS & 500 mS) that can be selected by setting the SCR.3 bit. When SCR.3 = 0 (default), the 500 mS period time is selected; when SCR.3 = 1, the 250 mS period time is selected. Watchdog Timer (WDT) The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program from unknown errors. The WDT is enabled when the corresponding option code bit of the WDT is set to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset. The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, and the WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 5. - 12 - W741E260 Divider0 Fosc Q1 Q2 HEF.0 S Q R ...Q9 Q10 Q11 Q12 Q13 Q14 R R R R EVF.0 IEF.0 Hold mode release (HCF.0) Divider0 interrupt (INT0) 1. Reset 2. CLR EVF, #01H 3. CLR DIVR0 PMF.3 R WDT Qw1 Qw2 Qw3 Qw4 R R R Fosc/16384 Fosc/1024 Overflow signal System Reset Enable /Disable Mask Option 1. Reset 2. CLR WDT Figure 5. Organization of Divider0 and Watchdog Timer Parameter Flag (PMF) The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows: 3 PMF Note: W means write only. 2 1 0 W Bit 0, Bit1, Bit2 Reserved Bit 3 = 0 The fundamental frequency of the watchdog timer is FOSC/1024. = 1 The fundamental frequency of the watchdog timer is FOSC/16384. Timer/Counter 1. Timer 0 (TM0) Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L (TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting), the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1 has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure 6. Publication Release Date: March 1998 Revision A2 - 13 - W741E260 If the Timer 0 clock input is FOSC/4: Desired time interval = (preset value +1) x 4 x 1/FOSC If the Timer 0 clock input is FOSC/1024: Desired time interval = (preset value +1) x 1024 x 1/FOSC Preset value: Decimal number of Timer 0 preset value, and FOSC: Clock oscillation frequency 1. Reset 2. CLR EVF, #02H 3. Reset MR0.3 to 0 4. MOV TM0L, R or MOV TM0H, R MR0.0 Fosc/1024 Fosc/4 Enable 1. Set MR0.3 to 1 2. MOV TM0, #I MOV TM0H, R Disable 8-bit Binary Down Counter (Timer 0) 4 8 MOV TM0L, R 4 HEF.1 S R Hold mode release (HCF.1) Q EVF.1 IEF.1 Timer 0 interrupt (INT1) 1. Reset 2. CLR EVF, #02H 3. Set MR0.3 to 1 4. MOV TM0, #I MOV TM0, #I Figure 6. Organization of Timer 0 2. Timer 1 (TM1) Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure . Timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: FOSC/64, FOSC, or an external clock from the RC.0 input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is FOSC. If an external clock is selected as the clock source of Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L, R or MOV TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set (MR1.3 = 1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into auto-reload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting. If the Timer 1 clock input is FT, then: - 14 - W741E260 Desired timer interval = (preset value +1) / FT Desired frequency for MFP output pin = FT / (preset value + 1) / 2 (Hz) Preset value: Decimal number of Timer 1 preset value, and FOSC: Clock oscillation frequency MOV TM1, #I MOV TM1H, R 8 1. MR1.3 = 1 2. MOV TM1, #I 4 Auto-reload buffer External clock via RC.0 MR1.1 Enable FT Fosc/64 Fosc MR1.0 8 bits 8-bit Binary Down Counter (Timer 1) Disable Reset Set MR1.3 to 1 MOV TM1, #I 1. MR1.3 = 0 4 MOV TM1L, R Underflow signal S R Q EVF.7 1. Reset 2. INT 7 accept 3. CLR EVF, #80H 4. Set MR1.3 to 1 5. MOV TM1, #I 2 circuit Reset MFP output pin MR1.2 MFP signal Figure 7. Organization of Timer 1 For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below. - 15 - Publication Release Date: March 1998 Revision A2 W741E260 3rd octave Tone frequency C C# T O N E D D# E F F# G G# A A# B 130.81 138.59 146.83 155.56 164.81 174.61 185.00 196.00 207.65 220.00 233.08 246.94 TM1 preset value & MFP frequency 7CH 75H 6FH 68H 62H 5DH 58H 53H 4EH 49H 45H 41H 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05 248.24 Tone frequency 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 4th octave TM1 preset value & MFP frequency 3EH 3AH 37H 34H 31H 2EH 2BH 29H 26H 24H 22H 20H 260.06 277.69 292.57 309.13 327.68 372.36 390.09 420.10 443.81 442.81 468.11 496.48 Tone frequency 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77 5th octave TM1 preset value & MFP frequency 1EH 1CH 1BH 19H 18H 16H 15H 14H 13H 12H 11H 10H 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76 Note: Central tone is A4 (440 Hz). Mode Register 0 (MR0) Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows: 3 MR0 Note: W means write only. 2 1 0 W W Bit 0 = 0 =1 Bit 3 = 0 =1 The fundamental frequency of Timer 0 is FOSC/4. The fundamental frequency of Timer 0 is FOSC/1024. Timer 0 stops down-counting. Timer 0 starts down-counting. Bit 1 & Bit 2 are reserved Mode Register 1 (MR1) Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows: 3 MR1 Note: W means write only. 2 W 1 W 0 W W - 16 - W741E260 Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC. = 1 The internal fundamental frequency of Timer 1 is FOSC/64. Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock. = 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin. Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin. = 1 The specified frequency of Timer 1 is delivered at the MFP output pin. Bit 3 = 0 Timer 1 stops down-counting. = 1 Timer 1 starts down-counting. Input/Output Ports RA, RB Port RA consists of pins RA.0 to RA.3 and Port RB consists of pins RB.0 to RB.3. At initial reset, input/output ports RA and RB are both in input mode. When RA and RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or RB can be specified as input or output mode independently by the PM1 and PM2 registers. The MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV RB, R operate the output functions. For more details, refer to the instruction table and Figure 8. Input/Output Pin of the RA(RB) Vdd PM0.0 (or PM0.1) Output Buffer DATA BUS Enable I/O PIN RA.n(RB.n) PM1.n (or PM2.n) MOV RA, R (or MOV RB, R) Instruction Enable MOVA R, RA (or MOVA R, RB) instruction Figure 8. Architecture of Input/Output Pins - 17 - Publication Release Date: March 1998 Revision A2 W741E260 Port Mode 0 Register (PM0) The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction. The bit descriptions are as follows: 3 PM0 w 2 w 1 w 0 w Note: W means write only. Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type. Bit 1 = 0 RB port is CMOS output type. Bit 1 = 1 RB port is NMOS open drain output type. Bit 2 = 0 RC port pull-high resistor is disabled. Bit 2 = 1 RC port pull-high resistor is enabled. Bit 3 = 0 RD port pull-high resistor is disabled. Bit 3 = 1 RD port pull-high resistor is enabled. Port Mode 1 Register (PM1) The port mode 1 register is organized as 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit descriptions are as follows: 3 PM1 Note: W means write only. 2 w 1 w 0 w w Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin At initial reset, port RA is input mode (PM1 = 1111B). Port Mode 2 Register (PM2) The port mode 2 register is organized as 4-bit binary register (PM2.0 to PM2.3). PM2 can be used to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit descriptions are as follows: 3 PM2 w 2 w 1 w 0 w Note: W means write only. - 18 - W741E260 Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin At initial reset, the port RB is input mode (PM2 = 1111B). Input Ports RC & RD Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. Each pin of port RC and port RD can be connected to a pull-up resistor, which is controlled by the port mode 0 register (PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change on the specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register 0 (PSR0) records the status of ports RC, i.e., any signal changes on the pins that make up the port. PSR0 can be read out and cleared by the MOV R, PSR0, and CLR PSR0 instructions. In addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will cause the device to exit the stop mode. Refer to Figure 9 and the instruction table for more details. The RD port is used as input port only, it has no hold mode release, wake-up stop mode or interrupt functions. Port Status Register 0 (PSR0) Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows: 3 PSR0 R 2 R 1 R 0 R Note: R means read only. Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Signal change at RC.0 Signal change at RC.1 Signal change at RC.2 Signal change at RC.3 Port Enable Flag (PEF) The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be used to release the hold mode or perform interrupt function, the content of the PEF must be set first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows: 3 PEF w 2 w 1 w 0 w Note: W means write only. - 19 - Publication Release Date: March 1998 Revision A2 W741E260 PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt. PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt. PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt. PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt. DATA BUS PM0.2 Signal change detector PEF.0 D ck R Q PSR0.0 RC.0 HEF.2 PEF.1 PM0.2 Signal change detector D ck R Q PSR0.1 EVF.2 D ck R IEF.2 Q HCF.2 RC.1 INT 2 PEF.2 PM0.2 Signal change detector D ck R Q PSR0.2 RC.2 CLR EVF, #I Reset PEF.3 PM0.2 Signal change detector D ck R Q PSR0.3 RC.3 SEF.0 Falling edge detector SEF.1 Falling edge detector Reset MOV PEF, #I CLR PSR0 Wake up from STOP mode SEF.2 Falling edge detector SEF.3 Falling edge detector Figure 9. Architecture of Input Port RC Output Port RE When the MOV RE, R instruction is executed, the data in the RAM will be output to port RE and it provides a high sink current to drive LEDs. MFP Output Pin (MFP) The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (MR1). The configuration of MFP is shown in Figure 9. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal from among DC, 4096Hz, 2048Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (when using a 32.768 KHz crystal). The MOV MFP, #I instruction is used to specify the - 20 - W741E260 modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown below. (Fosc = 32.768 KHz) R7 R6 R5 R4 R3 R2 R1 R0 FUNCTION 0 0 0 00 0 0 0 1 0 0 0 01 0 0 0 1 0 0 0 10 0 0 0 1 0 0 0 11 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 Low level 128 Hz 64 Hz 8 Hz 4 Hz 2 Hz 1 Hz High level 128 Hz 64 Hz 8 Hz 4 Hz 2 Hz 1 Hz 2048 Hz 2048 Hz * 128 Hz 2048 Hz * 64 Hz 2048 Hz * 8 Hz 2048 Hz * 4 Hz 2048 Hz * 2 Hz 2048 Hz * 1 Hz 4096 Hz 4096 Hz * 128 Hz 4096 Hz * 64 Hz 4096 Hz * 8 Hz 4096 Hz * 4 Hz 4096 Hz * 2 Hz 4096 Hz * 1 Hz - 21 - Publication Release Date: March 1998 Revision A2 W741E260 Interrupts The W741E260 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and one external interrupt source (port RC) for W741C260 body or three internal interrupt sources (Divider 0, Timer 0, Timer 1) and two external interrupt sources ( port RC, INT pin) for W741C250 body. Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily and interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt subroutine, the C will enter hold mode again. The operation flow chart is shown in Figure 11. The control diagram is shown below. Initial Reset Enable Divider 0 overflow signal EN INT MOV IEF, #I S R Q EVF.0 IEF.0 EVF.1 IEF.1 EVF.2 IEF.2 EVF.4 IEF.4 EVF.7 IEF.7 Interrupt Process Circuit Interrupt Vector Generator 004H 008H 00CH 014H 020H Timer 0 underflow signal S R Q Port RC signal change S R Q Divider 1 overflow signal S R Q Timer 1 underflow signal S R Q Initial Reset Disable CLR EVF, #I instruction DIS INT instruction Figure 10. Interrupt Event Control Diagram Interrupt Enable Flag (IEF) The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these interrupts is accepted, the corresponding to the bit of the event flag will be reset, but the other bits are unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or EN INT is executed again. Otherwise, these interrupts can be disabled by executing DIS INT instruction. The bit descriptions are as follows: - 22 - W741E260 7 IEF w 6 5 4 w 3 2 w 1 w 0 w Note: W means write only. IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0. IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0. IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC. IEF.3 is reserved. IEF.4 = 1 Interrupt 4 is accepted by overflow from the Divider 1 for W741C260 body. Interrupt 4 is accepted by a falling edge signal at the INT pin for W741C250 body. IEF.5 & IEF.6 are reserved. IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1. Stop Mode Operation In stop mode, all operations of the C cease (excluding the operation of the sub-oscillator and divider 1 when the dual-clock operation mode is selected). The C enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated (by a falling signal on the RC port for W741C260 body or by a falling signal on the RC port or a low level on the INT pin for W741C250 body). When the designated signal is accepted, the C awakens and executes the next instruction (if the corresponding bits of IEF and PEF have been set, It will enter the interrupt service routine after stop mode released). To prevent erroneous execution, the NOP instruction should follow the STOP command. But In the dual-clock slow operation mode, the STOP instruction will disable the main-oscillator oscillating; the C system is still operated by the sub-oscillator. Stop Mode Wake-up Enable Flag for RC Port (SEF) The stop mode wake-up flag for port RC is organized as an 4-bit binary register (SEF.0 to SEF.3). Before port RC may be used to make the device exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows: 3 SEF Note: W means write only. 2 w 1 w 0 w w SEF.0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0 SEF.1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1 SEF.2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2 SEF.3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3 - 23 - Publication Release Date: March 1998 Revision A2 W741E260 Hold Mode Operation In hold mode, all operations of the C cease, except for the operation of the oscillator, Timer, Divider and LCD driver. The C enters hold mode when the HOLD instruction is executed. The hold mode can be released in one of five ways: by the action of timer 0, timer 1, divider 0, divider 1, the RC port. Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release conditions. For more details, refer to the instruction-set table and the following flow chart. Divider 0, Divider 1, Timer 0, Timer 1, Signal Change at RC Port Yes In HOLD Mode? No Interrupt Enable? Yes No Interrupt Enable? Yes No IEF Flag Set? Yes Reset EVF Flag Execute Interrupt Service Routine (Note) No IEF Flag Set? Yes Reset EVF Flag Execute Interrupt Service Routine Yes No HEF Flag Set? No (Note) Disable interrupt Disable interrupt HOLD PC <- (PC+1) Note: The bit of EVF corresponding to the interrupt signal will be reset. Figure 11. Hold Mode and Interrupt Operation Flow Chart - 24 - W741E260 Hold Mode Release Enable Flag (HEF) The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I instruction. The bit descriptions are as follows: 7 HEF Note: W means write only. 6 5 4 w 3 2 w 1 w 0 w w HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released. HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released. HEF.2 = 1 Signal change at port RC causes Hold mode to be released. HEF.3 is reserved. HEF.4 = 1 Overflow from the Divider 1 causes Hold mode to be released for W741C260 body. Falling edge signal at the INT pin causes Hold mode to be released for W741C250 body. HEF.5 & HEF.6 are reserved. HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released. Hold Mode Release Condition Flag (HCF) The hold mode release condition flag is organized as a 8-bit binary register (HCF.0 to HCF.7). It indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset by the CLR EVF or MOV HEF, #I (HEF = 0) instructions. When EVF and HEF have been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows: 7 HCF Note: R means read only. 6 5 R 4 R 3 2 R 1 R 0 R HCF.0 = 1 Hold mode was released by overflow from the divider 0. HCF.1 = 1 Hold mode was released by underflow from the timer 0. HCF.2 = 1 Hold mode was released by a signal change at port RC. HCF.3 is reserved. HCF.4 = 1 Hold mode was released by overflow from the divider 1 for W741C260 body. Hold mode was released by a falling edge signal at the INT pin for W741C250 body. HCF.5 = 1 Hold mode was released by underflow from the timer 1. HCF.6 and HCF.7 are reserved. - 25 - Publication Release Date: March 1998 Revision A2 W741E260 Event Flag (EVF) The event flag is organized as a 8-bit binary register (EVF.0 to EVF.7). It is set by hardware and reset by CLR EVF, #I instruction or the occurrence of an interrupt. The bit descriptions are as follows: 7 EVF R 6 5 4 R 3 2 R 1 R 0 R Note: R means read only. EVF.0 = 1 Overflow from divider 0 occurred. EVF.1 = 1 Underflow from timer 0 occurred. EVF.2 = 1 Signal change at port RC occurred. EVF.3 is reserved. EVF.4 = 1 Overflow from divider 1 occurred for W741C260 body. Falling edge signal at the INT pin occurred for W741C250 body. EVF.5 & EVF.6 are reserved. EVF.7 = 1 Underflow from Timer 1 occurred. Reset Function The W741E260 is reset either by a power-on reset or by using the external RES pin. The initial state of the W741E260 after the reset function is executed is described below. Program Counter (PC) TM0, TM1 MR0, MR1, PAGE registers PSR0 registers IEF, HEF, HCF, PEF, EVF, SEF flags SCR register Timer 0 input clock Timer 1 input clock MFP output Input/output ports RA, RB Output port RE RA & RB ports output type RC & RD ports pull-high resistors Input clock of the watchdog timer LCD display Segment output mode 000H Reset Reset Reset Reset Reset FOSC/4 FOSC Low Input mode High CMOS type Disable FOSC/1024 OFF LCD drive output - 26 - W741E260 LCD Controller/Driver The W741E260 can directly drive an LCD with 32 segment output pins and 4 common output pins for a total of 32 x 4 dots. Option codes can be used to select one of five options for the LCD driving mode: static, 1/2 Bias 1/2 duty, 1/2 Bias 1/3 duty, 1/3 Bias 1/3 duty, or 1/3 Bias 1/4 duty (see Figure 13). The alternating frequency of the LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. In addition, option codes can also be used to set up four of the LCD driver output pins (segment 0 to segment 31) as a DC output port. The structure of the LCD alternating frequency (FLCD) is shown in Figure 12. Fosc or Fosc/32 Fs Fw/64 Fw/128 Fw/256 Fw/512 Fw Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Mask Option (Single/Dual Clock) Selector FLCD Figure 12. LCD Alternating Frequency (FLCD) Circuit Diagram Data Bus Option Codes LCD frequency selection Fw Clock Generator FLCD LCD Mode Controller LCD drive mode selection LCD DATA RAM (32 x 4 bits) MOV LCDM,#I instruction LCD duty & bias DH1 DH2 VDD VSS LCD Voltage Controller Commom Driver LCD waveform Segment Driver/Controller VDD1 to 3 COM0 to 3 SEG0 to 31 Figure 13. LCD Driver/Controller Circuit Diagram - 27 - Publication Release Date: March 1998 Revision A2 W741E260 When Fw = 32.768 KHz, the LCD frequency is as shown in the table below. LCD Frequency Fw/512 (64 Hz) Fw/256 (128 Hz) Fw/128 (256 Hz) Fw/64 (512 Hz) Static 64 128 256 512 1/2 Duty 32 64 128 256 1/3 Duty 21 43 85 171 1/4 Duty 16 32 64 128 Corresponding to the 32 LCD drive output pins, there are 32 LCD data RAM segments (LCDR00 to LCDR1F). Instructions such as MOV LCDR, #I; MOV WR, LCDR; MOV LCDR, WR; and MOV LCDR, ACC are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the segment output pins automatically without program control. When the bit value of the LCD data RAM is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," LCD is turned off. The contents of the LCD data RAM (LCDR) are sent out through the segment0 to segment31 pins by a direct memory access. The relation between the LCD data RAM and segment/common pins is shown below. LCD Data RAM LCDR00 LCDR01 . . . LCDR1E LCDR1F Output Pin SEG0 SEG1 . . . SEG30 SEG31 COM3 bit 3 0/1 0/1 . . . 0/1 0/1 COM2 bit 2 0/1 0/1 . . . 0/1 0/1 COM1 bit 1 0/1 0/1 . . . 0/1 0/1 COM0 bit 0 0/1 0/1 . . . 0/1 0/1 The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction turns the LCD display off. At initial reset, all the LCD segments are lit. When the initial reset state ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON must be executed. When the drive output pins are used as DC output ports (setting by option codes, please refer the user's manual of ASM741S assembler for more detail), CMOS output type or NMOS output type can be selected by executing the instruction MOV LCDM, #I. The relationship between the LCD data RAM and segment/common pins is shown below. The data in LCDR00 are transferred to the corresponding segment output port (SEG3 to SEG0) by a direct memory access. The other LCD data RAM segments can be used as normal data RAM to store data. LCD Data RAM LCDR00 LCDR03-LCDR01 LCDR04 LCDR07-LCDR05 . . . LCDR1C LCDR1F-LCDR1D Output Pin SEG3-SEG0 SEG7-SEG4 . . . SEG31-SEG30 Bit 3 SEG3 SEG7 . . . SEG31 Bit 2 SEG2 SEG6 . . . SEG30 Bit 1 SEG1 SEG5 . . . SEG29 Bit 0 SEG0 SEG4 . . . SEG28 - - 28 - W741E260 The relationship between the LCD drive mode and the maximum number of drivable LCD segments is shown below. LCD Drive Mode STATIC 1/2 Bias 1/2 Duty 1/2 Bias 1/3 Duty 1/3 Bias 1/3 Duty 1/3 Bias 1/4 Duty Max. Number of Drivable LCD Segment 32 (COM0) 64 (COM0-COM1) 96 (COM0-COM2) 96 (COM0-COM2) 128 (COM0-COM3) Connection at Power Input Connect VDD3, VDD2 to VDD1 Connect VDD3 to VDD2 Connect VDD3 to VDD2 - LCD Output Mode Type Flag (LCDM) The LCD output mode type flag is organized as an 8-bit binary register (LCDM.0 to LCDM.7). These bits are used to control the LCD output pins architecture. When LCD output pins are set to DC output mode by option codes, the architecture of these output pins (segment 0 to segment 31) can be selected as CMOS or NMOS type. It is controlled by the MOV LCDM, #I instruction. The bit descriptions are as follows: 7 LCDM Note: W means write only. 6 w 5 w 4 w 3 w 2 w 1 w 0 w w LCDM.0 = 0 SEG0 to SEG3 work as CMOS output type. = 1 SEG0 to SEG3 work as NMOS output type. LCDM.1 = 0 SEG4 to SEG7 work as CMOS output type. = 1 SEG4 to SEG7 work as NMOS output type. LCDM.2 = 0 SEG8 to SEG11 work as CMOS output type. = 1 SEG8 to SEG11 work as NMOS output type. LCDM.3 = 0 SEG12 to SEG15 work as CMOS output type. = 1 SEG12 to SEG15 work as NMOS output type. LCDM.4 = 0 SEG16 to SEG19 work as CMOS output type. = 1 SEG16 to SEG19 work as NMOS output type. LCDM.5 = 0 SEG20 to SEG23 work as CMOS output type. = 1 SEG20 to SEG23 work as NMOS output type. LCDM.6 = 0 SEG24 to SEG27 work as CMOS output type. = 1 SEG24 to SEG27 work as NMOS output type. LCDM.7 = 0 SEG28 to SEG31 work as CMOS output type. = 1 SEG28 to SEG31 work as NMOS output type. The output waveforms for the five LCD driving modes are shown below. - 29 - Publication Release Date: March 1998 Revision A2 W741E260 Static Lighting System (Example) Normal Operating Mode VDD2 VDD1 VSS VDD2 VDD1 VSS VDD2 VDD1 VSS COM0 Unlit LCD driver outputs Lit LCD driver outputs 1/2 Bias 1/2 duty Lighting System (Example) Normal Operating Mode COM0 VDD2 VDD1 VSS VDD2 VDD1 VSS VDD2 VDD1 VSS COM1 LCD driver outputs for seg. on COM0, COM1 sides being unlit LCD driver outputs for only seg. on COM0 side being lit VDD2 VDD1 VSS - 30 - W741E260 1/2 Bias 1/2 duty Lighting System (Example) - Normal Operating Mode, continued LCD driver outputs for only seg. on COM1 side being lit LCD driver outputs for seg. on COM0, COM1 sides being lit VDD2 VDD1 VSS VDD2 VDD1 VSS 1/2 Bias 1/3 duty Lighting System (Example) Normal Operating Mode VDD2 VDD1 VSS VDD2 VDD1 VSS VDD2 VDD1 VSS VDD2 VDD1 VSS COM0 COM1 COM2 LCD driver outputs for all seg. on COM0,1,2 sides being unlit LCD driver outputs for only seg. on COM0 side being lit LCD driver outputs for only seg. on COM1 side being lit LCD driver outputs for only seg. on COM0,1 sides being lit VDD2 VDD1 VSS VDD2 VDD1 VSS VDD2 VDD1 VSS - 31 - Publication Release Date: March 1998 Revision A2 W741E260 1/2 Bias 1/3 duty Lighting System (Example) - Normal Operating Mode, continued LCD driver outputs for only seg. on COM2 side being lit LCD driver outputs for only seg. on COM0,2 sides being lit VDD2 VDD1 VSS VDD2 VDD1 VSS 1/3 Bias 1/3 duty Lighting System (Example) Normal Operating Mode COM0 VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS COM1 COM2 LCD driver outputs for all seg. on COM0,1,2 sides being unlit LCD driver outputs for only seg. on COM0 side being lit LCD driver outputs for only seg. on COM1 side being lit LCD driver outputs for seg. on COM0,2 sides being lit VDD3 VDD2 VDD1 VSS - 32 - W741E260 1/3 Bias 1/3 duty Lighting System (Example) - Normal Operating Mode, continued LCD driver outputs for seg. on COM1,2 sides being lit LCD driver outputs for seg. on COM0,1,2 sides being lit VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS 1/3 Bias 1/4 duty Lighting System (Example) Normal Operating Mode VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS COM0 COM1 COM2 COM3 LCD driver outputs for only seg. on COM0 side being lit LCD driver outputs for only seg. on COM1 side being lit VDD3 VDD2 VDD1 VSS - 33 - Publication Release Date: March 1998 Revision A2 W741E260 1/3 Bias 1/4 duty Lighting System (Example) - Normal Operating Mode, continued LCD driver outputs for seg. on COM0, COM1 sides being lit LCD driver outputs for seg. on COM1, COM2,3 sides being lit LCD driver outputs for seg. on COM1 COM2 sides being lit LCD driver outputs for seg. on COM0 COM2,3 sides being lit LCD driver outputs for seg. on COM0 COM1,2,3 sides being lit VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS - 34 - W741E260 The power connections for each LCD driving mode, which are determined by a mask option, are shown below. Static LCD Configuration 1/2 Bias LCD Configuration DH1 DH1 DH1, DH2 floating DH2 VSS DH2 VSS VDD VDD 0.1uF C H I P C H I P VDD VDD 0.1uF VDD1 VDD2 VDD3 VDD1 VDD2 VDD3 VDD1 = VDD2 = VDD3 = VDD VDD1 = 1/2 VDD, VDD2 = VDD3 = VDD 1/3 Bias LCD Configuration DH1 0.1uF DH2 VSS C H I P VDD VDD 0.1uF VDD1 VDD2 VDD3 VDD1 = 1/2 VDD, VDD2 = VDD, VDD3 = 3/2 VDD - 35 - Publication Release Date: March 1998 Revision A2 W741E260 LCD Configuration, continued 1/3 Bias LCD Configuration DH1 0.1uF DH2 VSS C H I P VDD VDD 0.1uF VDD1 VDD2 VDD3 VDD1 = 1/3 VDD, VDD2 = 2/3 VDD, VDD3 = VDD EEPROM Program/Erase Description The built-in program code memory of the W741E260 is the EEPROM structure. This memory can be programmed, erased and verified through the VPP, MODE and DATA pins. The on board program/erase connection is shown below. XTAL WHC4403 58 57 55 51 Xin1 Xout1 Vdd Mode W741E260 1 Vss 5 Vpp 6 Data 7 JP9 Figure 14. The W741E260 Program/Erase Configuration - 36 - W741E260 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage Temperature RATING -0.3 to +7.0 -0.3 to +7.0 120 0 to +70 -55 to +150 UNIT V V mW C C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC CHARACTERISTICS (VDD-VSS = 3.0V, Fm = 4.19 MHz, Fs = 32.768 KHz, Ta = 25 C, LCD on; unless otherwise specified) PARAMETER Op. Voltage Op. Current (Crystal type) SYM. VDD IOP1 CONDITIONS No load (Ext-V) In dual-clock normal operation No load (Ext-V) In dual-clock normal operation No load (Ext-V) In dual-clock slow operation and Fm is stopped Hold mode No load (Ext-V) In dual-clock normal operation Hold mode No load (Ext-V) In dual-clock normal operation Hold mode No load (Ext-V) In dual-clock slow operation and Fm is stopped Stop mode No load (Ext-V) In dual-clock normal operation Stop mode No load (Ext-V) In single-clock operation - MIN. 2.4 - TYP. 0.6 MAX. 5.5 2.5 UNIT V mA Op. Current (RC type) IOP2 - 1 4 mA Op. Current (Crystal type) IOP3 - 8.5 20 A Hold Current (Crystal type) Hold Current (RC type) IHM1 - 280 450 A IHM2 - 500 600 A Hold Current (Crystal type) Stop Current (Crystal type) Stop Current (Crystal type) Input Low Voltage IHM3 - 4.0 6 A ISM1 - 4.0 6 A ISM2 VIL VSS 0.1 - 2 0.3 VDD A V - 37 - Publication Release Date: March 1998 Revision A2 W741E260 DC Characteristics, continued PARAMETER Input High Voltage MFP Output Low Voltage MFP Output High Voltage Port RA, RB Output Low Voltage Port RA, RB Output high Voltage LCD Supply Current SEG0-SEG31 Sink Current (Used as LCD output) SEG0-SEG31 Drive Current (Used as LCD output) Segment output low voltage (Used as DC output) Segment output high voltage (Used as DC output) Port RE Sink Current Port RE Source Current Input Port Pull-up Resistor INT Pull-up Resistor RES Pull-up Resistor VPP Pull-down Resistor MODE Pull-down Resistor DATA Pull-down Resistor SYM. VIH VML VMH VABL VABH ILCD IOL1 CONDITIONS IOL = 3.5 mA IOH = 3.5 mA IOL = 2.0 mA IOH = 2.0 mA All Seg. ON VOL = 0.4V VLCD = 0.0V VOH = 2.4V VLCD = 3.0V IOL = 0.6 mA MIN. 0.7 VDD 2.4 2.4 0.4 TYP. - MAX. VDD 0.4 0.4 6 - UNIT V V V V V A A IOH1 0.3 - - A VSL - - 0.4 V VSH IOH = 3 A 2.4 - - V IEL IEH RCD RINT RRES RVPP RMODE RDATA VOL = 0.9V VOH = 2.4V Port RC, RD VDD = 5V VDD = 5V VDD = 5V 9 0.4 100 50 20 1.5 1.5 50 1.2 350 250 100 2 2 100 1000 1000 500 2.5 2.5 150 mA mA K K K M M K - 38 - W741E260 AC CHARACTERISTICS (VDD-VSS = 3.0V, Ta = 25 C; unless otherwise specified) PARAMETER SYM. CONDITIONS RC type MIN. 400 - TYP. 32.768 - MAX. 4000 4190 10 UNIT Op. Frequency FOSC Crystal type 1 (Option low speed type) Crystal type 2 (Option high speed type) KHz Frequency Deviation by Voltage Drop for RC Oscillator Instruction Cycle Time Reset Active Width Interrupt Active Width f f TI TRAW TIAW f(3V) - f(2.4V) f(3V) One machine cycle FOSC = 32.768 KHz FOSC = 32.768 KHz % 1 1 4/FOSC - - mS S S PAD ASSIGNMENT AND POSITIONS 2870 m 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 1 2 3 57 56 55 54 53 52 51 50 49 48 4 5 Y 4840 m 6 7 8 9 10 11 12 13 14 15 16 17 18 19 X (0,0) 47 46 45 44 43 42 41 40 39 20 38 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Note: The chip substrate must be connected to system ground (VSS). - 39 - Publication Release Date: March 1998 Revision A2 W741E260 PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 PAD NAME RE2 RE3 VSS VPP DATA COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 X -1227.80 -1227.80 -1227.80 -1223.25 -1234.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -1227.80 -975.80 -845.80 -715.80 -585.80 -455.80 -325.80 -195.80 -65.80 64.20 194.20 324.20 454.20 584.20 714.20 844.20 974.20 Y 1810.50 1680.50 1550.50 1079.40 656.85 36.20 -93.80 -223.80 -353.80 -483.80 -613.80 -743.80 -873.80 -1003.80 -1133.80 -1263.80 -1393.80 -1523.80 -1653.80 -1783.80 -1913.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 -2163.80 PAD NO. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 PAD NAME SEG28 SEG29 SEG30 SEG31 VDD3 VDD2 VDD1 DH2 DH1 MODE XOUT2 XIN2 VDD XOUT1 XIN1 RES INT MFP RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RC0 RC1 RC2 RC3 RD0 RD1 RD2 RD3 RE0 RE1 X 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1226.20 1040.30 910.30 780.30 650.30 520.30 390.30 260.30 130.30 0.30 -129.70 -259.70 -389.70 -519.70 -649.70 -779.70 -909.70 Y -1913.80 -1783.80 -1653.80 -1523.80 -1393.80 -1263.80 -1133.80 -1003.80 -873.80 -112.50 640.50 770.50 900.50 1030.50 1160.50 1290.50 1420.50 1550.50 1680.50 1810.50 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 2141.70 - 40 - W741E260 TYPICAL APPLICATION CIRCUIT Vcc VDD RA0 Output Signal RA3 RB0 RB1 RB2 RB3 RC0 RC1 RC2 RC3 RD0 RD1 RD2 RD3 COM3 SEG0 SEG31 0.1 uF COM0 LCD PANEL (1/3 Bias 1/4 Duty) DH1 DH2 VDD1 VDD2 VDD3 Connect to capacitor and VDD to generate LCD voltage Vcc RES 0.1 uF XOUT1 XIN1 XOUT2 32.768 KHz RE0 RE1 RE2 RE3 MFP Vcc XIN2 VSS 470 W 0.1 uF - 41 - Publication Release Date: March 1998 Revision A2 W741E260 INSTRUCTION SET TABLE Symbol Description ACC: ACC.n: WR: PAGE: MR0: MR1: PM0: PM1: PM2: PSR0: PSR1: R: LCDR: R.n: I: L: CF: ZF: PC: TM0L: TM0H: TM1L: TM1H: TABL: TABH: IEF.n: HCF.n: HEF.n: SEF.n: PEF.n: EVF.n: ! =: &: ^: EX: : [PAGE*10H+()]: [P()]: Accumulator Accumulator bit n Working Register Page Register Mode Register 0 Mode Register 1 Port Mode 0 Port Mode 1 Port Mode 2 Port Status Register 0 Port Status Register 1 Memory (RAM) of address R LCD data RAM of address LDR Memory bit n of address R Constant parameter Branch or jump address Carry Flag Zero Flag Program Counter Low nibble of the Timer 0 counter High nibble of the Timer 0 counter Low nibble of the Timer 1 counter High nibble of the Timer 1 counter Low nibble of the look-up table address buffer High nibble of the look-up table address buffer Interrupt Enable Flag n HOLD mode release Condition Flag n HOLD mode release Enable Flag n STOP mode wake-up Enable Flag n Port Enable Flag n Event Flag n Not equal AND OR Exclusive OR Transfer direction, result Contents of address PAGE(bit2, bit1, bit0)*10H+() Contents of port P - 42 - W741E260 INSTRUCTION SET TABLE 1 Mnemonic Arithmetic ADD ADD ADDR ADDR ADC ADC ADCR ADCR ADU ADU ADUR ADUR SUB SUB SUBR SUBR SBC SBC SBCR SBCR INC DEC R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R R Function ACC(R) + (ACC) ACC(WR) + I ACC, R(R) + (ACC) ACC, WR(WR) + I ACC(R) + (ACC) + (CF) ACC(WR) + I + (CF) ACC, R(R) + (ACC) + (CF) ACC, WR(WR) + I + (CF) ACC(R) + (ACC) ACC(WR) + I ACC, R(R) + (ACC) ACC, W R(WR) + I ACC(R) - (ACC) ACC(WR) - I ACC, R(R) - (ACC) ACC, WR(WR) - I ACC(R) - (ACC) - (CF) ACC(WR) - I - (CF) ACC, R(R) - (ACC) - (CF) ACC, WR(WR) - I - (CF) ACC, R(R) + 1 ACC, R(R) - 1 Flag Affected ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF ZF ZF ZF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 43 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 1, continued Mnemonic Logic Operations ANL ANL ANLR ANLR ORL ORL ORLR ORLR XRL XRL XRLR XRLR Branch JMP JB0 JB1 JB2 JB3 JZ JNZ JC JNC DSKZ DSKNZ SKB0 SKB1 SKB2 SKB3 L L L L L L L L L R R R R R R R, ACC WR, #I R, ACC W, R #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I Function ACC(R) & (ACC) ACC(WR) & I ACC, R(R) & (ACC) ACC, WR(WR) & I ACC(R) (ACC) ACC(WR) I ACC, R(R) (ACC) ACC, WR(WR) I ACC(R) EX (ACC) ACC(WR) EX I ACC, R(R) EX (ACC) ACC, WR(WR) EX I PC10~PC0L10~L0 PC10~PC0L10~L0; if ACC.0 = "1" PC10~PC0L10~L0; if ACC.1 = "1" PC10~PC0L10~L0; if ACC.2 = "1" PC10~PC0L10~L0; if ACC.3 = "1" PC10~PC0L10~L0; if ACC = 0 PC10~PC0L10~L0; if ACC ! = 0 PC10~PC0L10~L0; if CF = "1" PC10~PC0L10~L0; if CF != "1" ACC, R(R) - 1; skip if ACC = 0 ACC, R(R) - 1; skip if ACC != 0 Skip if R.0 = "1" Skip if R.1 = "1" Skip if R.2 = "1" Skip if R.3 = "1" Flag Affected ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ZF, CF ZF, CF 1 1 1 1 1 1 - 44 - W741E260 Instruction Set Table 1, continued Mnemonic Data Move MOV MOV MOVA MOVA MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVA MOVA MOVA MOVA MOV MOV MOV MOV MOVA MOV MOV MOV MOV MOVA MOV MOVA MOVA WR, R R, WR WR, R R, WR R, ACC ACC, R R, #I WR, @R @R, WR TABL, R TABH, R R WR, #I R, RA R, RB R, RC R, RD RA, R RB R RE, R MFP, #I R, PAGE PAGE, R MR0, #I MR1, #I PAGE, #I R, CF CF, R R,HCFL R,HCFH WR(R) R(WR) Function Flag Affected Cycle 1 1 ACC, WR(R) ACC, R(WR) R(ACC) ACC(R) RI WR[PR(bit2, bit1, bit0)x10H +(R)] [PR(bit2, bit1, bit0)x10H +(R)]WR TABL(R) TABH(R) R[(TABH) x 10H + (TABL)] WR [(I6 ~ I0) x 10H + (ACC)] ACC, R[RA] ACC, R[RB] ACC, R[RC] ACC, R[RD] [RA](R) [RB](R) [RE](R) [MFP] I ACC, RPAGE (Page Register) PAGE(R) MR0I MR1I PAGEI ACC.0, R.0CF CF(R.0) ACC, RHCF0~HCF3 ACC, RHCF4~HCF7 ZF ZF ZF 1 1 1 1 1 2 2 1 1 2 2 Input & Output ZF ZF ZF ZF 1 1 1 1 1 1 1 1 ZF 1 1 1 1 1 ZF CF ZF ZF 1 1 1 1 Flag & Register - 45 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 1, continued CLR SET MOV MOV MOV CLR MOV MOV MOV MOV MOV MOVA CLR SET CLR CLR CLR CLR SHRC Mnemonic PMF, #I PMF, #I PM0, #I PM1, #I PM2, #I EVF, #I PEF, #I IEF, #I HEF, #I SEF, #I SCR, #I R, PSR0 PSR0 CF CF DIVR0 DIVR1 WDT R Function Clear Parameter Flag if In = 1 Set Parameter Flag if In = 1 Port Mode 0 I Port Mode 1 I Port Mode 2 I Clear Event Flag if In = 1 Set/Reset Port Enable Flag Set/Reset Interrupt Enable Flag Set/Reset HOLD mode release Enable Flag Set/Reset STOP mode wake-up Enable Flag for RC port SCRI ACC, RPort Status Register 0 Clear Port Status Register 0 Set Carry Flag Clear Carry Flag Clear the last 4-bit of the Divider 0 Clear the last 4-bit of the Divider 1 Clear WatchDog Timer ACC.n, R.n(R.n+1); ACC.3, R.30; CFR.0 Flag Affected Cycle 1 NOTE 2 1 NOTE 2 1 1 1 1 1 1 1 1 1 NOTE 1 ZF CF CF 1 1 1 1 1 1 NOTE 1 1 Shift & Rotate ZF, CF 1 RRC R ACC.n, R.n(R.n+1); ACC.3, R.3CF; CFR.0 ZF, CF 1 SHLC R ACC.n, R.n(R.n-1); ACC.0, R.00; CFR.3 ZF, CF 1 RLC R ACC.n, R.n(R.n-1); ACC.0, R.0CF; CFR.3 ZF, CF 1 - 46 - W741E260 Instruction Set Table 1, continued Mnemonic LCD MOV MOV MOV MOV MOV LCDON LCDOFF Timer MOV MOV MOV MOV MOV MOV Subroutine CALL L TM0L, R TM0H, R TM0, #I TM1L, R TM1H, R TM1, #I TM0L(R) TM0H(R) Timer 0 set TM1L(R) TM1H(R) Timer 1 set LCDR, #I WR, LCDR LCDR, WR LCDR, ACC LCDM, #I LCDR I Function Flag Affected Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WR(LCDR) LCDR(WR) LCDR(ACC) Select LCD output mode type LCD ON LCD OFF STACK (PC)+1; PC10 ~ PC0 L10 ~ L0 (PC) STACK Enter Hold mode Enter Stop mode No Operation RTN Other HOLD STOP NOP EN DIS Note: 1 1 1 1 1 1 INT INT Enable Interrupt Function Disable Interrupt Function 1. These instructions are available in W741C260 body, but inhibited in W741C250 body. 2. The bit0, bit1 and bit2 of PMF are reserved in W741C250 and W741C260 body. - 47 - Publication Release Date: March 1998 Revision A2 W741E260 INSTRUCTION SET TABLE 2 ADC R, ACC Add R to ACC with CF 0 0 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC (R) + (ACC) + (CF) The contents of the data memory location addressed by R6 to R0, ACC, and CF are binary added and the result is loaded into the ACC. CF & ZF Add immediate data to WR with CF 0 0 0 0 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: ADC WR, #I Machine Code: Machine Cycle: Operation: Description: 1 ACC (WR) + I + (CF) The contents of the Working Register (WR), I and CF are binary added and the result is loaded into the ACC. CF & ZF Add R to ACC with CF 0 0 0 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: ADCR R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (R) + (ACC) + (CF) The contents of the data memory location addressed by R6 to R0, ACC, and CF are binary added and the result is placed in the ACC and the data memory. CF & ZF Flag Affected: - 48 - W741E260 Instruction Set Table 2, continued ADCR WR, #I Add immediate data to WR with CF 0 0 0 0 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Code: Machine Cycle: Operation: Description: 1 ACC, WR (WR) + I + (CF) The contents of the Working Register (WR), I, CF are binary added and the result is placed in the ACC and the WR. CF & ZF Add R to ACC 0 0 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: ADD R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC (R) + (ACC) The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is loaded into the ACC. CF & ZF Add immediate data to WR 0 0 0 1 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: ADD WR, #I Machine Code: Machine Cycle: Operation: Description: 1 ACC (WR) + I The contents of the Working Register (WR) and the immediate data I are binary added and the result is loaded into the ACC. CF & ZF Flag Affected: - 49 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued ADDR R, ACC Add R to ACC 0 0 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (R) + (ACC) The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is placed in the ACC and the data memory. CF & ZF Add immediate data to WR 0 0 0 1 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: ADDR WR, #I Machine Code: Machine Cycle: Operation: Description: 1 ACC, WR (WR) + I The contents of the Working Register (WR) and the immediate data I are binary added and the result is placed in the ACC and the WR. CF & ZF Add R to ACC and Carry Flag unchange 0 0 1 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: ADU R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC (R) + (ACC) The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is loaded into the ACC. ZF Flag Affected: - 50 - W741E260 Instruction Set Table 2, continued ADU WR, #I Add immediate data to WR and Carry Flag unchange 0 0 1 0 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Code: Machine Cycle: Operation: Description: 1 ACC (WR) + I The contents of the Working Register (WR) and the immediate data I are binary added and the result is loaded into the ACC. ZF Add R to ACC and Carry Flag unchange 0 0 1 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: ADUR R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (R) + (ACC) The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is placed in the ACC and the data memory. ZF Add immediate data to WR and Carry Flag unchange 0 0 1 0 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: ADUR WR, #I Machine Code: Machine Cycle: Operation: Description: 1 ACC, WR (WR) + I The contents of the Working Register (WR) and the immediate data I are binary added and the result is placed in the WR and the ACC. ZF Flag Affected: - 51 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued ANL R, ACC And R to ACC 0 0 1 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC (R) & (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are ANDed and the result is loaded into the ACC. ZF And immediate data to WR 0 0 1 0 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: ANL WR, #I Machine Code: Machine Cycle: Operation: Description: 1 ACC (WR) & I The contents of the Working Register (WR) and the immediate data I are ANDed and the result is loaded into the ACC. ZF And R to ACC 0 0 1 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: ANLR R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (R) & (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are ANDed and the result is placed in the data memory and the ACC. ZF Flag Affected: - 52 - W741E260 Instruction Set Table 2, continued ANLR WR, #I And immediate data to WR 0 0 1 0 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Code: Machine Cycle: Operation: Description: 1 ACC, WR (WR) & I The contents of the Working Register (WR) and the immediate data I are ANDed and the result is placed in the WR and the ACC. ZF Call subroutine 0 1 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Flag Affected: CALL L Machine Code: Machine Cycle: Operation: 1 STACK (PC)+1; PC10 ~ PC0 L10 ~ L0 The next program counter (PC10 to PC0) is saved in the STACK and then the direct address (L10 to L0) is loaded into the program counter. A subroutine is called. Clear CF 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Description: CLR CF Machine Code: Machine Cycle: Operation: Description: Flag Affected: 1 Clear CF Clear Carry Flag to 0. CF - 53 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued CLR DIVR0 Reset the last 4 bits of the DIVideR 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 Machine Code: Machine Cycle: Operation: Description: 1 Reset the last 4 bits of the divider 0 When this instruction is executed, the last 4 bits of the divider 0 (14 bits) are reset. Reset the last 4 bits of the DIVideR 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 CLR DIVR1 Machine Code: Machine Cycle: Operation: Description: 1 Reset the last 4 bits of the divider 1 When this instruction is executed, the last 4 bits of the divider 1 (14 bits) are reset. This instruction is available in W741C260 body, but it is inhibited in W741C250 body. Clear ParaMeter Flag 0 0 0 1 0 1 1 0 1 0 0 0 I3 I2 I1 I0 CLR PMF, #I Machine Code: Machine Cycle: Operation: Description: 1 Clear Parameter Flag Description of each flag: I0, I1, I2 : Reserved I3 = 1 : The input clock of the watchdog timer is Fosc/1024. - 54 - W741E260 Instruction Set Table 2, continued CLR EVF, #I Clear EVent Flag 0 1 0 0 0 0 0 0 I7 I6 I5 I4 I3 I2 I1 I0 Machine Code: Machine Cycle: Operation: Description: 1 Clear event flag The condition corresponding to the data specified by I7 to I0 is controlled. I0~I7 I0 = 1 I1 = 1 I2 = 1 I3 I4 = 1 I5 & I6 I7 = 1 Mode after execution of instruction EVF0 caused by overflow from the divider 0 is reset. EVF1 caused by underflow from the timer 0 is reset. EVF2 caused by the signal change at port RC is reset. Reserved EVF4 caused by overflow from the divider 1 is reset for W741C260 body; EVF4 caused by the falling edge signal on INT pin is reset for W741C250 body. Reserved EVF7 caused by underflow from the timer 1 is reset. CLR PSR0 Clear Port Status Register 0 (RC port signal change flag) 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Machine Code: Machine Cycle: Operation: Description: 1 Clear Port Status Register 0 (RC port signal change flag) When this instruction is executed, the RC port signal change flag (PSR0) is cleared. Reset the last 4 bits of the WatchDog Timer 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 CLR WDT Machine Code: Machine Cycle: Operation: Description: 1 Reset the last 4 bits of the watchdog timer When this instruction is executed, the last 4 bits of the watchdog timer are reset. - 55 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued DEC R Decrement R content 0 1 0 0 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (R) - 1 Decrement the data memory content and load result into the ACC and the data memory. CF & ZF Disable Interrupt function 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 Flag Affected: DIS INT Machine Code: Machine Cycle: Operation: Description: DSKNZ R 1 Disable interrupt function Interrupt function is inhibited by executing this instruction. Decrement R content then skip if ACC ! = 0 0 1 0 0 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: 1 ACC, R (R) - 1; PC (PC) + 2 if ACC ! = 0 Decrement the data memory content and load result into the ACC and the data memory. If ACC ! = 0, the program counter is incremented by 2 and produces a skip. CF & ZF Description: Flag Affected: - 56 - W741E260 Instruction Set Table 2, continued DSKZ R Decrement R content then skip if ACC is zero 0 1 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: 1 ACC, R (R) - 1; PC (PC) + 2 if ACC = 0 Decrement the data memory content and load result into the ACC and the data memory. If ACC = 0, the program counter is incremented by 2 and produces a skip. CF & ZF Enable Interrupt function 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 Description: Flag Affected: EN INT Machine Code: Machine Cycle: Operation: Description: HOLD Machine Code: Machine Cycle: Operation: Description: 1 1 Enable interrupt function This instruction enables the interrupt function. Enter the HOLD mode 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Enter the HOLD mode The following two conditions cause the HOLD mode to be released. (1) An interrupt is accepted. (2) The HOLD release condition specified by the HEF is met. In HOLD mode, when an interrupt is accepted the HOLD mode will be released and the interrupt service routine will be executed. After completing the interrupt service routine by executing the RTN instruction, the C will enter HOLD mode again. - 57 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued INC R Increment R content 0 1 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (R) + 1 Increment the data memory content and load the result into the ACC and the data memory. CF & ZF Jump when bit 0 of ACC is "1" 1 0 0 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Flag Affected: JB0 L Machine Code: Machine Cycle: Operation: Description: 1 PC10 ~ PC0 L10 ~ L0; if ACC.0 = "1" If bit 0 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 0 of the ACC is "0," the program counter (PC) is incremented. Jump when bit 1 of ACC is "1" 1 0 0 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 JB1 L Machine Code: Machine Cycle: Operation: Description: 1 PC10 ~ PC0 L10 ~ L0; if ACC.1 = "1" If bit 1 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 1 of the ACC is "0," the program counter (PC) is incremented. - 58 - W741E260 Instruction Set Table 2, continued JB2 L Jump when bit 2 of ACC is "1" 1 0 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Code: Machine Cycle: Operation: Description: 1 PC10 ~ PC0 L10 ~ L0; if ACC.2="1" If bit 2 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 2 of the ACC is "0," the program counter (PC) is incremented. Jump when bit 3 of ACC is "1" 1 0 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 JB3 L Machine Code: Machine Cycle: Operation: Description: 1 PC10 ~ PC0 L10 ~ L0; if ACC.3 = "1" If bit 3 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 3 of the ACC is "0," the program counter (PC) is incremented. Jump when CF is "1" 1 1 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 JC L Machine Code: Machine Cycle: Operation: Description: 1 PC10 ~ PC0 L10 ~ L0; if CF = "1" If CF is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If the CF is "0," the program counter (PC) is incremented. - 59 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued JMP L Jump absolutely 0 1 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Code: Machine Cycle: Operation: Description: 1 PC10 ~ PC0 L10 ~ L0 PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and an unconditional jump occurs. Jump when CF is not "1" 1 1 0 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 JNC L Machine Code: Machine Cycle: Operation: Description: 1 PC10 ~ PC0 L10 ~ L0; if CF = "0" If CF is "0," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If CF is "1," the program counter (PC) is incremented. Jump when ACC is not zero 1 1 0 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 JNZ L Machine Code: Machine Cycle: Operation: Description: 1 PC10 ~ PC0 L10 ~ L0; if ACC ! = 0 If the ACC is not zero, PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If the ACC is zero, the program counter (PC) is incremented. - 60 - W741E260 Instruction Set Table 2, continued JZ L Jump when ACC is zero 1 1 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Code: Machine Cycle: Operation: Description: 1 PC10 ~ PC0 L10 ~ L0; if ACC = 0 If the ACC is zero, PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If the ACC is not zero, the program counter (PC) is incremented. LCD ON 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 LCDON Machine Code: Machine Cycle: Operation: Description: LCDOFF Machine Code: Machine Cycle: Operation: Description: 1 LCD ON Turn on LCD display. LCD OFF 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 LCD OFF Turn off LCD display. - 61 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV ACC, R Move R content to ACC 0 1 0 0 1 1 1 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC (R) The contents of the data memory location addressed by R6 to R0 are loaded into the ACC. ZF Move R.0 content to CF 0 1 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: MOV CF, R Machine Code: Machine Cycle: Operation: Description: 1 CF (R.0) The bit 0 content of the data memory location addressed by R6 to R0 is loaded into CF. CF Flag Affected: - 62 - W741E260 Instruction Set Table 2, continued MOV HEF, #I Set/Reset Hold mode release Enable Flag 0 1 0 0 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0 Machine Code: Machine Cycle: Operation: Description: 1 Hold mode release enable flag control I0~I7 I0 = 1 I1 = 1 I2 = 1 I3 Operation The HEF0 is set so that overflow from the divider 0 caused the HOLD mode to be released. The HEF1 is set so that underflow from the Timer 0 caused the HOLD mode to be released. The HEF2 is set so that signal change at port RC caused the HOLD mode to be released. Reserved The HEF4 is set so that overflow from the divider 1 caused the HOLD mode to be released for W741C260 body; The HEF4 is set so that the falling edge signal at the INT pin caused the HOLD mode to be released for W741C250 body. Reserved The HEF7 is set so that underflow from the Timer 1 caused the HOLD mode to be released. I4 = 1 I5 & I6 I7 = 1 - 63 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV IEF, #I Set/Reset Interrupt Enable Flag 0 1 0 1 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0 Machine Code: Machine Cycle: Operation: Description: 1 Interrupt Enable flag Control The interrupt enable flag corresponding to the data specified by I7-I0 is controlled: I0~I7 I0 = 1 Operation The IEF0 is set so that interrupt 0 (overflow from the divider 0) is accepted. The IEF1 is set so that interrupt 1 (underflow from the Timer 0) is accepted. The IEF2 is set so that interrupt 2 (signal change at port RC) is accepted. Reserved The IEF4 is set so that interrupt 4 (overflow from the divider 1) is accepted for W741C260 body; the IEF4 is set so that interrupt 4 (falling edge signal at the INT pin) is accepted for the W741C250 body. Reserved The IEF7 is set so that interrupt 7 (underflow from the Timer 1) is accepted. I1 = 1 I2 = 1 I3 I4 = 1 I5 & I6 I7 = 1 MOV LCDM, #I Select LCD output Mode type 0 0 0 0 0 0 1 1 I7 I6 I5 I4 I3 I2 I1 I0 Machine Code: Machine Cycle: Operation: Description: 1 Select LCD output mode type When LCD output pins are set to DC output mode, user can select CMOS or NMOS as output type. I0~I7 = 0 => CMOS type; I0~I7 = 1 => NMOS type. - 64 - W741E260 Instruction Set Table 2, continued MOV LCDR, ACC Move ACC content to LCDR 0 0 0 0 0 1 1 D4 D3 D2 D1 D0 0 0 0 0 Machine Code: Machine Cycle: Operation: Description: 1 LCDR (ACC) The contents of the ACC are loaded to the LCD data RAM (LCDR) location addressed by D4 to D0. Load WR content to LCDR 0 1 0 0 0 1 0 D4 D3 D2 D1 D0 W3 W2 W1 W0 MOV LCDR, WR Machine Code: Machine Cycle: Operation: Description: 1 LCDR (WR) The contents of the WR are loaded to the LCD data RAM (LCDR) location addressed by D4 to D0. Load immediate data to LCDR 0 0 0 0 0 1 0 D4 D3 D2 D1 D0 I3 I2 I1 I0 MOV LCDR, #I Machine Code: Machine Cycle: Operation: Description: 1 LCDR I The immediate data I are loaded to the LCD data RAM (LCDR) location addressed by D4 to D0. - 65 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV MFP, #I Modulation Frequency Pulse generator 0 0 0 1 0 0 1 0 I7 I6 I5 I4 I3 I2 I1 I0 Machine Code: Machine Cycle: Operation: Description: 1 [MFP] I If the bit 2 of MR1 is "0," the waveform specified by I7 to I0 is delivered at the MFP output pin (MFP). The relation between the waveform and immediate data I is as follows: I5~I0 Signal I0 = 1 Fosc 256 I1 = 1 Fosc 512 I2 = 1 Fosc 4096 I3 = 1 Fosc 8192 I4 = 1 Fosc 16384 I5 = 1 Fosc 32768 I7 0 0 1 1 I6 0 1 0 1 Signal Low High Fosc/16 Fosc/8 - 66 - W741E260 Instruction Set Table 2, continued MOV MR0, #I Load immediate data to Mode Register 0 (MR0) 0 0 0 1 0 0 1 1 1 0 0 0 I3 I2 I1 I0 Machine Code: Machine Cycle: Operation: Description: 1 MR0 I The immediate data I are loaded to the MR0. MR0 bits description: bit 0 = 0 The fundamental frequency of Timer 0 is Fosc/4 = 1 The fundamental frequency of Timer 0 is Fosc/1024 bit 1 bit 2 bit 3 Reserved Reserved = 0 Timer 0 stop down-counting = 1 Timer 0 start down-counting - 67 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV MR1, #I Load immediate data to Mode Register 1 (MR1) 0 0 0 1 0 0 1 1 0 0 0 0 I3 I2 I1 I0 Machine Code: Machine Cycle: Operation: Description: 1 MR1 I The immediate data I are loaded to the MR1. MR1 bit description: = 0 The internal fundamental frequency of Timer 1 is Fosc = 1 The internal fundamental frequency of Timer 1 is Fosc/64 = 0 The fundamental frequency source of Timer 1 is internal clock = 1 The fundamental frequency source of Timer 1 is external clock via RC.0 input pin = 0 The specified waveform of the MFP generator is delivered at the MFP output pin = 1 The specified frequency of the Timer 1 is delivered at the MFP output pin = 0 Timer 1 stop down-counting = 1 Timer 1 start down-counting bit0 bit1 bit2 bit3 - 68 - W741E260 Instruction Set Table 2, continued MOV PAGE, #I Machine Code: Machine Cycle: Operation: Description: Load immediate data to Page Register 0 1 0 1 0 1 1 0 1 0 0 0 I3 I2 I1 I0 1 Page Register I The immediate data I are loaded to the PR. Bit 3 is reserved. Bit 0, bit 1, and bit 2 indirect addressing mode preselect bits: bit2 0 0 0 0 1 1 1 1 bit1 0 0 1 1 0 0 1 1 bit0 0 1 0 1 0 1 0 1 = Page 0 (00H~0FH) = Page 1 (10H~1FH) = Page 2 (20H~2FH) = Page 3 (30H~3FH) = Page 4 (40H~4FH) = Page 5 (50H~5FH) = Page 6 (60H~6FH) = Page 7 (70H~7FH) - 69 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV PEF, #I Set/Reset Port Enable Flag 0 1 0 0 0 0 1 1 0 0 0 0 I3 I2 I1 I0 Machine Code: Machine Cycle: Operation: Description: 1 Port enable flag control The data specified by I can cause HOLD mode to be released or an interrupt to occur. The signal change on port RC is specified. I0~I7 I0 = 1 I1 = 1 I2 = 1 I3 = 1 Signal change at port RC RC0 RC1 RC2 RC3 MOV PM0, #I Machine Code: Machine Cycle: Operation: Description: Set/Reset Port Mode 0 register 0 1 0 1 0 0 1 1 0 0 0 0 I3 I2 I1 I0 1 Set/Reset Port mode 0 register I0 = 0: RA port is CMOS type; I0 = 1: RA port is NMOS type. I1 = 0: RB port is CMOS type; I1 = 1: RB port is NMOS type. I2 = 0: RC port pull-high resistor is disabled; I2 = 1: RC port pull-high resistor is enabled. I3 = 0: RD port pull-high resistor is disabled; I3 = 1: RD port pull-high resistor is enabled. - 70 - W741E260 Instruction set table 2, continued MOV PM1, #I Machine Code: Machine Cycle: Operation: Description: RA port independent Input/Output control 0 1 0 1 0 1 1 1 0 0 0 0 I3 I2 I1 I0 1 RA port 4 pins input/output control is independent. I0 = 0: RA.0 is output pin; I0 = 1: RA.0 is input pin. I1 = 0: RA.1 is output pin; I1 = 1: RA.1 is input pin. I2 = 0: RA.2 is output pin; I2 = 1: RA.2 is input pin. I3 = 0: RA.3 is output pin; I3 = 1: RA.3 is input pin. Default condition RA port is input mode (PM = 1111B). RB port independent Input/Output control 0 1 0 1 0 1 1 1 1 0 0 0 I3 I2 I1 I0 MOV PM2, #I Machine Code: Machine Cycle: Operation: Description: 1 RB port 4 pins input/output control is independent. I0 = 0: RB.0 is output pin; I0 = 1: RB.0 is input pin. I1 = 0: RB.1 is output pin; I1 = 1: RB.1 is input pin. I2 = 0: RB.2 is output pin; I2 = 1: RB.2 is input pin. I3 = 0: RB.3 is output pin; I3 = 1: RB.3 is input pin. Default condition RB port is input mode (PM2 = 1111B). - 71 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV R, ACC Move ACC content to R 0 1 0 1 1 0 0 1 1 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 R (ACC) The contents of the ACC are loaded to the data memory location addressed by R6 to R0. Input RA port data to ACC & R 0 1 0 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 MOVA R, RA Machine Code: Machine Cycle: Operation: Description: 1 ACC , R [RA] The data on port RA are loaded into the data memory location addressed by R6 to R0 and the ACC. ZF Input RB port data to ACC & R 0 1 0 1 1 0 1 1 1 R6 R5 R4 R3 R2 R1 R0 Flag Affected: MOVA R, RB Machine Code: Machine Cycle: Operation: Description: 1 ACC , R [RB] The data on port RB are loaded into the data memory location addressed by R6 to R0 and the ACC. ZF Flag Affected: - 72 - W741E260 Instruction Set Table 2, continued MOVA R, RC Machine Code: Machine Cycle: Operation: Description: Input RC port data to ACC & R 0 1 0 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 1 ACC , R [RC] The input data on the input port RC are loaded into the data memory location addressed by R6 to R0 and the ACC. ZF Input RD port data to ACC & R 0 1 0 0 1 0 1 1 1 R6 R5 R4 R3 R2 R1 R0 Flag Affected: MOVA R, RD Machine Code: Machine Cycle: Operation: Description: 1 ACC , R [RD] The input data on the input port RD are loaded into the data memory location addressed by R6 to R0 and the ACC. ZF Move WR content to R 1 1 1 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: MOV R, WR Machine Code: Machine Cycle: Operation: Description: 1 R (WR) The contents of the WR are loaded to the data memory location addressed by R6 to R0. - 73 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV R, #I Load immediate data to R 1 0 1 1 1 I3 I2 I1 I0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 RI The immediate data I are loaded to the data memory location addressed by R6 to R0. Output R content to RA port 0 1 0 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 MOV RA, R Machine Code: Machine Cycle: Operation: Description: 1 [RA] (R) The data in the data memory location addressed by R6 to R0 are output to the port RA. Output R content to RB port 0 1 0 1 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0 MOV RB, R Machine Code: Machine Cycle: Operation: Description: 6 1 [RB] (R) The contents of the data memory location addressed by R6 to R0 are output to the port RB. Output R content to port RE 0 1 0 1 1 1 1 0 0 R6 R5 R4 R3 R2 R1 R0 MOV RE, R Machine Code: Machine Cycle: Operation: Description: 1 [RE] (R) The contents of the data memory location addressed by R6 to R0 are output to port RE. - 74 - W741E260 Instruction Set Table 2, continued MOV SCR, #I Machine Code: Machine Cycle: Operation: Description: System Clock Register control 0 1 0 1 0 1 0 0 0 0 0 0 I3 I2 I1 I0 1 System clock control If the operation mode is the dual clock operation selected by the option codes, the system clock and oscillator can be arranged by controlling the system clock register. This command is just for the W741C260 body. SCR bits decription: Bit 0 = 0, Fosc=Fm = 1, Fosc=Fs = 0, main oscillator is enabled = 1, main oscillator is disabled Reserved = 0, divider 1 is 14-stage = 1, divider 1 is 13-stage Bit 1 Bit 2 Bit 3 MOV SEF, #I Machine Code: Machine Cycle: Operation: Description: Set/Reset STOP mode waked-up Enable Flag for port RC 0 1 0 1 0 0 1 0 0 0 0 0 I3 I2 I1 I0 1 Set/reset STOP mode wake-up enable flag for port RC The data specified by I cause a wake-up from the STOP mode. The fallingedge signal on port RC can be specified independently. I0~I7 I0 = 1 I1 = 1 I2 = 1 I3 = 1 Falling edge signal at port RC RC0 RC1 RC2 RC3 - 75 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV TM0, #I Machine Code: Machine Cycle: Operation: Description: MOV TM0L, R Machine Code: Machine Cycle: Operation: Description: Timer 0 set 0 0 0 1 0 0 0 0 I7 I6 I5 I4 I3 I2 I1 I0 1 Timer 0 set The data specified by I7 to I0 is loaded to the Timer 0 to start the timer. Move R content to TM0L 0 0 0 1 0 1 0 0 0 R6 R5 R4 R3 R2 R1 R0 1 TM0L (R) The contents of the data memory location addressed by R6 to R0 are loaded into the TM0L. Move R content to TM0H 0 0 0 1 0 1 0 0 1 R6 R5 R4 R3 R2 R1 R0 MOV TM0H, R Machine code: Machine Cycle: Operation: Description: 1 TM0H (R) The contents of the data memory location addressed by R6 to R0 are loaded into the TM0H. Timer 1 set 0 0 0 1 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0 MOV TM1, #I Machine Code: Machine Cycle: Operation: Description: 1 Timer 1 set The data specified by I7 to I0 is loaded to the Timer 1 to start the timer. - 76 - W741E260 Instruction Set Table 2, continued MOV TM1L, R Machine Code: Machine Cycle: Operation: Description: Move R content to TM1L 0 0 0 1 0 1 0 1 0 R6 R5 R4 R3 R2 R1 R0 1 TM1L (R) The contents of the data memory location addressed by R6 to R0 are loaded into the TM1L. Move R content to TM1H 0 0 0 1 0 1 0 1 1 R6 R5 R4 R3 R2 R1 R0 MOV TM1H, R Machine code: Machine Cycle: Operation: Description: 1 TM1H (R) The contents of the data memory location addressed by R6 to R0 are loaded into the TM1H. Load LCDR content to WR 0 1 0 0 0 1 1 D4 D3 D2 D1 D0 W3 W2 W1 W0 MOV WR, LCDR Machine Code: Machine Cycle: Operation: Description: 1 WR (LCDR) The contents of the LCD data RAM location addressed by D4 to D0 are loaded to the WR. Move R content to WR 1 1 1 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 MOV WR, R Machine Code: Machine Cycle: Operation: Description: 1 WR (R) The contents of the data memory location addressed by R6 to R0 are loaded to the WR. - 77 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV WR, @R Indirect load from R to WR 1 1 0 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 2 WR [PR (bit2, bit1, bit0) x 10H + (R)] The data memory contents of address [PR (bit2, bit1, bit0) x 10H + (R)] are loaded to the WR. Indirect load from WR to R 1 1 0 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 MOV @R, WR Machine Code: Machine Cycle: Operation: Description: 2 [PR (bit2, bit1, bit0) x 10H + (R)] WR The contents of the WR are loaded to the data memory location addressed by [PR (bit2, bit1, bit0) x 10H + (R)] . Move R content to Page Register 0 1 0 1 1 1 1 0 1 R6 R5 R4 R3 R2 R1 R0 MOV PAGE, R Machine Code: Machine Cycle: Operation: Description: 1 PR (R) The contents of the data memory location addressed by R6 to R0 are loaded to the PR. - 78 - W741E260 Instruction Set Table 2, continued MOVA R, CF Move CF content to ACC.0 & R.0 0 1 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC.0, R.0 (CF) The content of CF is loaded to bit 0 of the data memory location addressed by R6 to R0 and the ACC. The other bits of the data memory and ACC are reset to "0." ZF Move HCF4~7 to ACC & R 0 1 0 0 1 0 0 1 1 R6 R5 R4 R3 R2 R1 R0 Flag Affected: MOVA R, HCFH Machine Code: Machine Cycle: Operation: Description: 1 ACC, R HCF4~7 The contents of HCF bit 4 to bit 7 (HCF4 to HCF7) are loaded to the data memory location addressed by R6 to R0 and the ACC. The ACC contents and the meaning of the bits after execution of this instruction are as follows: Bit 0 Bit 1 Bit 2 Bit 3 HCF4: "1" when the HOLD mode is released by overflow from Divide r 1 for the W741C260 body; HCF4: "1" when the HOLD mode is released by the falling edge signal at the INT pin for the W741C250 body. HCF7: "1" when the HOLD mode is released by underflow from Timer 1. Reserved. Reserved. Flag Affected: ZF - 79 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOVA R, HCFL Machine Code: Machine Cycle: Operation: Description: Move HCF0~3 to ACC & R 0 1 0 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 1 ACC, R HCF0~3 The contents of HCF bit 0 to bit 3 (HCF0 to HCF3) are loaded to the data memory location addressed by R6 to R0 and the ACC. The ACC contents and the meaning of the bits after execution of this instruction are as follows: Bit 0 Bit 1 Bit 2 Bit 3 HCF0: "1" when the HOLD mode is released by overflow from the Divider 0. HCF1: "1" when the HOLD mode is released by underflow from Timer 0. HCF2: "1" when the HOLD mode is released by a signal change on port RC. Reserved. Flag Affected: MOVA R, PAGE Machine Code: Machine Cycle: Operation: Description: ZF Move Page Register content to ACC & R 0 1 0 1 1 1 1 1 1 R6 R5 R4 R3 R2 R1 R0 1 ACC , R (Page Register) The contents of the Page Register (PR) are loaded to the data memory location addressed by R6 to R0 and the ACC. ZF Flag Affected: - 80 - W741E260 Instruction Set Table 2, continued MOVA R, PSR0 Machine Code: Machine Cycle: Operation: Description: Move Port Status Register 0 content to ACC & R 0 1 0 0 1 1 1 1 0 R6 R5 R4 R3 R2 R1 R0 1 ACC, R RC port signal change flag (PSR0) The contents of the RC port signal change flag (PSR0) are loaded to the data memory location addressed by R6 to R0 and the ACC. When the signal changes on any pin of the RC port, the corresponding signal change flag should be set to 1. Otherwise, it should be 0. ZF Move WR content to ACC & R 0 1 1 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: MOVA R, WR Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (WR) The contents of the WR are loaded to the ACC and the data memory location addressed by R6 to R0. ZF Move R content to ACC & WR 0 1 1 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: MOVA WR, R Machine Code: Machine Cycle: Operation: Description: 1 ACC, WR (R) The contents of the data memory location addressed by R6 to R0 are loaded to the WR and the ACC. ZF Flag Affected: - 81 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued MOV TABL, R Machine Code: Machine Cycle: Operation: Description: Move R content to TABL 1 0 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 1 TABL (R) The contents of the data memory location addressed by R6 to R0 are loaded into the TABL. Move R content to TABH 1 0 0 1 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0 MOV TABH, R Machine code: Machine Cycle: Operation: Description: 1 TABH (R) The contents of the data memory location addressed by R6 to R0 are loaded into the TABH. Move look-up table ROM addressed by TABL and TABH to R 1 0 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 MOVC R Machine code: Machine Cycle: Operation: Description: 2 WR [(TABH) x 10H + (TABL)] The contents of the look-up table ROM location addressed by TABH and TABL are loaded to R. - 82 - W741E260 Instruction Set Table 2, continued MOVC WR, #I Machine code: Machine Cycle: Operation: Description: Move look-up table ROM addressed by #I and ACC to WR 1 0 1 0 1 W3 W2 W1 W0 I6 I5 I4 I3 I2 I1 I0 2 WR [(I6 ~ I0) x 10H + (ACC)] The contents of the look-up table ROM location addressed by I6 to I0 and the ACC are loaded to R. No Operation 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP Machine Code: Machine Cycle: Operation: ORL R, ACC 1 No Operation OR R to ACC 0 0 1 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC (R) (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are ORed and the result is loaded into the ACC. ZF Flag Affected: - 83 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued ORL WR , #I OR immediate data to WR 0 0 1 1 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Code: Machine Cycle: Operation: Description: 1 ACC (WR) I The contents of the Working Register (WR) and the immediate data I are ORed and the result is loaded into the ACC. ZF OR R to ACC 0 0 1 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: ORLR R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (R) (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are ORed and the result is placed in the data memory and the ACC. ZF OR immediate data to WR 0 0 1 1 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: ORLR WR , #I Machine Code: Machine Cycle: Operation: Description: 1 ACC, WR (WR) I The contents of the Working Register(WR) and the immediate data I are ORed and the result is placed in the WR and the ACC. ZF Flag Affected: - 84 - W741E260 Instruction Set Table 2, continued RLC R Rotate Left R with CF 0 1 0 0 1 1 0 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC.n, R.n (R.n-1); ACC.0, R.0 CF; CF R.3 The contents of the ACC and the data memory location addressed by R6 to R0 are rotated left one bit, bit 3 is rotated into CF, and CF rotated into bit 0 (LSB). The same contents are loaded into the ACC. CF & ZF Rotate Right R with CF 0 1 0 0 1 1 0 1 1 R6 R5 R4 R3 R2 R1 R0 Flag Affected: RRC R Machine Code: Machine Cycle: Operation: Description: 1 ACC.n, R.n (R.n+1); ACC.3, R.3 CF; CF R.0 The contents of the ACC and the data memory location addressed by R6 to R0 are rotated right one bit, bit 0 is rotated into CF, and CF is rotated into bit 3 (MSB). The same contents are loaded into the ACC. CF & ZF Return from subroutine 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Flag Affected: RTN Machine Code: Machine Cycle: Operation: Description: 1 (PC) STACK The program counter (PC10 to PC0) is restored from the stack. A return from a subroutine occurs. - 85 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued SBC R, ACC Subtract ACC from R with Borrow 0 0 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC (R) - (ACC) - (CF) The contents of the ACC and CF are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is loaded into the ACC. CF & ZF Subtract immediate data from WR with Borrow 0 0 0 0 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: SBC WR, #I Machine Code: Machine Cycle: Operation: Description: 1 ACC (WR) - I - (CF) The immediate data I and CF are binary subtracted from the contents of the WR and the result is loaded into the ACC. CF & ZF Subtract ACC from R with Borrow 0 0 0 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: SBCR R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (R) - (ACC) - (CF) The contents of the ACC and CF are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is placed in the ACC and the data memory. CF & ZF Flag Affected: - 86 - W741E260 Instruction Set Table 2, continued SBCR WR, #I Subtract immediate data from WR with Borrow 0 0 0 0 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (WR) - I - (CF) The immediate data I and CF are binary subtracted from the contents of the WR and the result is placed in the ACC and the WR. CF & ZF Set CF 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 Flag Affected: SET CF Machine Code: Machine Cycle: Operation: Description: Flag Affected: SET PMF, #I 1 Set CF Set Carry Flag to 1. CF Set ParaMeter Flag 0 0 0 1 0 1 1 0 0 0 0 0 I3 I2 I1 I0 Machine Code: Machine Cycle: Operation: Description: 1 Set Parameter Flag Description of each flag: I0, I1, I2 : Reserved I3 = 1 : The input clock of the watchdog timer is Fosc/16384. - 87 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued SHLC R SHift Left R with CF and LSB = 0 0 1 0 0 1 1 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 ACC.n, R.n (R.n-1); ACC.0, R.0 0; CF R.3 The contents of the ACC and the data memory location addressed by R6 to R0 are shifted left one bit, but bit 3 is shifted into CF, and bit 0 (LSB) is replaced with "0." The same contents are loaded into the ACC. CF & ZF SHift Right R with CF and MSB = 0 0 1 0 0 1 1 0 1 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: SHRC R Machine Code: Machine Cycle: Operation: Description: 1 ACC.n, R.n (R.n+1); ACC.3, R.3 0; CF R.0 The contents of the ACC and the data memory location addressed by R6 to R0 are shifted right one bit, but bit 0 is shifted into CF, and bit 3 (MSB) is replaced with "0." The same contents are loaded into the ACC. CF & ZF If bit 0 of R is equal to 1 then skip 1 0 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: SKB0 R Machine Code: Machine Cycle: Operation: Description: 1 PC (PC) + 2; if R.0 = 1"1" If bit 0 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 0 of R is not equal to 1, the program counter (PC) is incremented. - 88 - W741E260 Instruction Set Table 2, continued SKB1 R If bit 1 of R is equal to 1 then skip 1 0 0 0 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Code: Machine Cycle: Operation: Description: 1 PC (PC) + 2; if R.1 = 1"1" If bit 1 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 1 of R is not equal to 1, the program counter (PC) is incremented. If bit 2 of R is equal to 1 then skip 1 0 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 SKB2 R Machine Code: Machine Cycle: Operation: Description: 1 PC (PC) + 2; if R.2 = 1"1" If bit 2 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 2 of R is not equal to 1. The program counter (PC) is incremented. If bit 3 of R is equal to 1 then skip 1 0 0 0 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0 SKB3 R Machine Code: Machine Cycle: Operation: Description: 1 PC (PC) + 2; if R.3 = 1"1" If bit 3 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 3 of R is not equal to 1, the program counter (PC) is incremented. - 89 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued STOP Machine Code: Machine Cycle: Operation: Description: Enter the STOP mode 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 STOP oscillator Device enters STOP mode. When the falling edge signal of RC port is accepted, the C will wake up and execute the next instruction. Subtract ACC from R 0 0 0 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 SUB R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC (R) - (ACC) The contents of the ACC are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is loaded into the ACC. CF & ZF Subtract immediate data from WR 0 0 0 1 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: SUB WR , #I Machine Code: Machine Cycle: Operation: Description: 1 ACC (WR) - I The immediate data I are binary subtracted from the contents of the WR and the result is loaded into the ACC. CF & ZF Flag Affected: - 90 - W741E260 Instruction Set Table 2, continued SUBR R, ACC Machine Code: Machine Cycle: Operation: Description: Subtract ACC from R 0 0 0 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 1 ACC, R (R) - (ACC) The contents of the ACC are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is placed in the ACC and the data memory. CF & ZF Subtract immediate data from WR 0 0 0 1 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: SUBR WR, #I Machine Code: Machine Cycle: Operation: Description: 1 ACC, WR (WR) - I The immediate data I are binary subtracted from the contents of the WR and the result is placed in the ACC and the WR. CF & ZF Exclusive OR R to ACC 0 0 1 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: XRL R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC (R) EX (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are exclusive-ORed and the result is loaded into the ACC. ZF Flag Affected: - 91 - Publication Release Date: March 1998 Revision A2 W741E260 Instruction Set Table 2, continued XRL WR, #I Exclusive OR immediate data to WR 0 0 1 1 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Code: Machine Cycle: Operation: Description: 1 ACC (WR) EX I The contents of the Working Register (WR) and the immediate data I are exclusive-ORed and the result is loaded into the ACC. ZF Exclusive OR R to ACC 0 0 1 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Flag Affected: XRLR R, ACC Machine Code: Machine Cycle: Operation: Description: 1 ACC, R (R) EX (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are exclusive-ORed and the result is placed in the data memory and the ACC. ZF Exclusive OR immediate data to WR 0 0 1 1 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0 Flag Affected: XRLR WR, #I Machine Code: Machine Cycle: Operation: Description: 1 ACC, WR (WR) EX I The contents of the Working Register(WR) and the immediate data I are exclusive-ORed and the result is placed in the WR and the ACC. ZF Flag Affected: - 92 - W741E260 PACKAGE DIMENSIONS 80-Lead QFP HD D 80 65 1 64 E EH 24 41 25 e b 40 c 2 AA See Detail F Seating Plane 1 y A L L1 Detail F Symbol Dimension in inches Dimension in mm Min. Nom Max. Min. Nom Max. 0.130 0.004 0.107 0.112 0.012 0.014 0.004 0.006 0.546 0.551 0.782 0.787 0.025 0.031 0.728 0.964 0.039 0.740 0.976 0.047 0.117 0.018 0.010 0.556 0.10 2.73 0.30 0.10 13.87 2.85 0.35 0.15 2.97 0.45 0.25 3.30 A A1 A2 b c D E e HD HE L L1 y 0 14.00 14.13 20.00 20.13 0.80 0.95 0.792 19.87 0.037 0.752 0.988 0.055 0.103 0.004 0.65 18.49 24.49 1.00 2.21 18.80 19.10 24.80 25.10 1.20 2.40 1.40 2.62 0.10 0.087 0.094 0 12 0 12 - 93 - Publication Release Date: March 1998 Revision A2 W741E260 NOTES: Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 94 - |
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